1. Field of the Invention
The present invention relates to the field of semiconductor device manufacturing, and in particular to a photolithography method for reducing effects of lens aberration.
2. Description of the Related Art
The manufacture of complex semiconductor devices involves defining multiple layers of device features onto a substrate using photolithography techniques. To achieve proper electrical contact between the different layers or levels of device features, each layer must be accurately aligned with the previous underlying layer. Misalignment of a layer of device features with respect to the previous underlying layer can result in unintended openings or shorts between device features on different levels, causing failure of the entire product.
Alignments of layers of device features has conventionally been achieved through the use of overlay targets, typically box-in-box targets, located in the kerf surrounding the outer edge of a chip product area on a semiconductor wafer. In addition, the alignment within each single layer of device features has conventionally been achieved through the use of global alignment marks located in the kerf of non-chip product area at the outer edge of a semiconductor wafer and the use of the local alignment marks located in the kerf between chips on a semiconductor wafer. Once the box-in-box targets, the local alignment marks and the global alignment marks are proper aligned, it is assumed that a single layer of the device features within the product field will also proper alignment. Nevertheless, it has been observed that significant overlay errors such as asymmetry, distortion and poor critical diameter (CD) uniformity of the transferred patterns can occur within the product area even when all the described alignment marks are proper alignment and the box-in-box overlay error is driven to zero. The unintended phenomenon can be result of lens aberration from lens failure such as, for example, projection lens within the optical projection system of a photolithography apparatus and the common lens aberrations exhibiting spherical aberration, astigmatism, coma, field curvature or distortion.
In FIG. 1, a schematic diagram of step-scanner 5, one type of photolithography apparatus, is illustrated and abbreviated to scanner 5 hereinafter. In a photolithography process performed by the scanner 5, light source (not shown) projects light L through slit field S of masking blades 10, through the transparent portions of a pattern on reticle 12 disposed on reticle platform 14, through projection lens (not shown) in optic projection system 16, focusing onto wafer 18 disposed on wafer platform 20. During the described photolithography process, reticle platform 14 and wafer platform 20 move simultaneously and light L scans the reticle 12 to transfer patterns thereon onto wafer 18 step-by-step. Movements of reticle platform 14 and wafer platform 20 can be the same or opposite upon the practical arrangement of the optic projection system 16.
In FIG. 2a to FIG. 2d, portions of the conventional photolithography process for fabricating a trench-type dynamic random access memory (DRAM) are illustrated and the photolithography apparatus used here is, for example, the described scanner 5.
In FIG. 2a, a first reticle 12a is provided and disposed onto the reticle platform 14 (not shown). In the first reticle 12a, overlay targets 100 located at corners thereof and specific transfer patterns shown in area 105 are illustrated. The specific transfer patterns shown in area 105 can be, for example, a plurality of pairs of first rectangular transparent region 120 symmetrically disposed therein, surrounded by the opaque region 110. Each first rectangular transparent region 120 has short sides and long sides respectively parallel to the X and Y orientations shown in FIG. 2a. 
In FIG. 2b, a wafer 18a having a notch 130 thereon as an orientation mark is provided. The orientation mark here is not restricted to the notch 130 of conventional 8 inch wafers and can be also, for example, a flat side of 6 inch wafers. In addition, a resist layer 133 formed by photosensitive materials is coated on the wafer 18a and other coated layers, for example anti-reflection coating (ARC) layer, for enhancing the photolithography result can be further formed thereon. Next, the wafer 18a coated with the resist layer 133 is disposed on the wafer platform 20 with the orientation mark 130 parallel to the Y orientation shown in FIG. 2b. 
A first photolithography (not shown) is performed after proper alignment of the particular layer by moving the reticle platform 14 (not shown) and the wafer platform 20 in the same or opposite orientation parallel to the scanning direction 135, parallel to the long sides of the first rectangular transparent region 120, to transfer patterns of the first transparent rectangular region 120 onto the wafer 18a. After subsequent development and etching, first transferred patterns 120′ for fabricating trench-capacitors, for example, are formed on the wafer 18a and shown in region 140 of FIG. 2b. The first transferred patterns 120′ are slightly larger than the target CD of the first rectangular transparent regions 120 and poor critical dimensions (CD) of the first transferred patterns 120′ in the short axis and asymmetry of each pair of first transferred patterns 120′ affected by the lens aberration can be observed. Thus, a trench-type capacitor with the first transferred patterns 120′ can be formed on the wafer 18a by subsequent fabricating processes (not shown).
In FIG. 2c, the previous reticle on the reticle platform 14 (not shown) is replaced with a second reticle 12b having overlay targets 100′ located at corners thereof and a plurality of second rectangular transparent regions 170 surrounded by the opaque region 160. Each second transparent rectangular region 170 has long sides and short sides respectively parallel to the X and Y orientations in FIG. 2c. 
In FIG. 2d, the previous wafer 18a, having trench-type capacitors thereon with the first transferred pattern 120′ is again provided. In addition, a resist layer 183 formed by photosensitive materials is coated on the wafer 18a and other coated layers, for example anti-reflection coating (ARC) layer, for enhancing the photolithography result can be further formed thereon.
Next, the wafer 18a coated with the resist layer 183 thereon is disposed on the wafer platform 20 and the orientation mark 130 thereof is parallel to the Y orientation shown in FIG. 2d. Then a second photolithography (not shown) is performed after proper alignment of the particular layer by moving the reticle platform 14 (not shown) and the wafer platform 20 in the same or opposite orientation parallel to the scanning direction 165, parallel to the short sides of the second rectangular transparent region 170, to transfer patterns of the second transparent rectangular region 170 for fabricating, for example, active areas onto the wafer 18a. Thus, active areas for receiving ion implantation with the second transferred patterns 170′ can be formed on the wafer 18a by performing subsequent fabricating processes (not shown). After subsequent development and etching (not shown), active areas with second transferred patterns 170′ are formed on the wafer 18a shown in region 180 of FIG. 2d, for example, respectively overlying a pair of the underlying trench capacitors with the first transferred patterns 120′.
Thus, overlap regions D between the active areas with second transferred patterns 170′ overlying the underlying trench capacitors with first transferred patterns 120′ vary from one to the other. Poor critical dimension (CD) uniformity of the first transferred patterns 120′ and asymmetry thereof impacted by lens aberration are observed. Thus, overlay errors occur and electrical performance of subsequently formed device features are also affected.